1. Field of the Invention
The present invention relates to a method for forming wiring in a semiconductor device, and more particularly to a method for forming wiring in a silicon substrate of the semiconductor device.
2. Description of the Prior Art
As generally known in the art, a semiconductor device is fabricated in a stacked structure, and wiring is correspondingly formed in a multi-layer structure that is easy in design.
When the above noted semiconductor device with stacked structure is fabricated, surface planarization is more important than anything else because it affects the following photo and etch processes.
Accordingly, a dual damascene process has been widely employed in order to achieve a surface planarization in recent wiring processes, in particular, in metal wiring processes.
As generally known in the art, the dual damascene process includes the steps of: forming a contact hole for an electrical connection with lower wiring in an interlayer insulating layer, forming a trench for defining upper wiring region, depositing wiring materials to fill the contact hole and the trench, and chemical-mechanical polishing (CMP) the wiring materials in order to expose the interlayer insulating layer.
However, as regards the conventional wiring formation method, including the dual damascene process, although many studies have been undertaken regarding processing technology, wiring formation has been neglected. Accordingly, wiring has been complicated and a step differential has become larger following the increase of the degree of integration of the semiconductor device, resulting in several problems regarding the characteristics of the semiconductor device and the fabrication process.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming wiring in a semiconductor device, which is easy for designing wiring in the semiconductor device and can obviate problems incurred due to step differential.
In order to accomplish this object, there is provided a method for forming wiring in a semiconductor device, comprising the steps of: forming a trench in a desired place on a silicon substrate, forming a thermal oxidation layer on the surface of the trench, forming wiring by filling a conductive layer in the lower part of the trench, forming an insulating layer on the wiring, removing the thermal oxidation layer over the insulating layer, forming an epitaxial silicon layer so that the trench is filled completely, forming a contact hole exposing the wiring by etching the epitaxial silicon layer and the insulating layer, forming an insulating spacer on the side walls of the contact hole, and forming a wiring plug in the contact hole in which the insulating layer has been formed.
In the above embodiment of the present invention, the trench has a depth of 0.5 to 1.0 xcexcm.
Further, the step of forming the trench comprises: depositing a first insulating layer and a second insulating layer sequentially on the silicon substrate, exposing a predetermined part of the substrate by etching the first and second insulating layers, and etching the exposed part of the substrate.
Also, the first insulating layer is composed of thermal oxidation layer, and the second layer is composed of nitride layer.
Additionally, the insulating layer is composed of materials having high dry-etch and wet-etch selection ratios.
Also, in this embodiment of the present invention, the step of forming the spacer comprises: forming a thermal oxidation layer on the surface of the contact hole and the substrate by thermal oxidizing the resultant structure of the substrate in which the contact hole has been formed and then blanket etching the thermal oxidation layer.
In accordance with another embodiment of the present invention, there is provided a method for forming wiring in a semiconductor device, comprising the steps of: depositing a first insulating layer and a second insulating layer sequentially on the silicon substrate, exposing a predetermined part of the substrate by etching the first and second insulating layers, forming a trench by etching the exposed part of the substrate, forming a third insulating layer on the surface of the trench by thermal oxidation, depositing wiring materials to fill the trench, forming wiring in the lower part of the trench by etching back the wiring materials, forming a fourth insulating layer on the wiring, removing the third insulating layer on the fourth insulating layer, forming an epitaxial silicon layer so that the trench can be completely filled, forming a contact hole exposing the wiring by etching the epitaxial silicon layer and the fourth insulating layer, forming a fifth insulating layer at a side wall of the contact hole, removing the first and second insulating layers, and forming a wiring plug in the contact hole in which the fifth insulating layer has been formed.
In this embodiment of the present invention, the first insulating layer, the third insulating layer and the fifth insulating layer are all made of thermal oxidation layer.
Also, the fourth insulating layer is made of materials having a high dry-etch and wet-etch selection rate with respect to the second insulating layer and the third insulating layer.
Further, in this embodiment of the present invention, the step of forming the fifth insulating layer comprises: thermal oxidizing the resultant structure of the substrate in which the contact hole has been formed and then blanket etching the fifth insulating layer formed by the thermal oxidation in order to form a spacer.